The present invention relates to semiconductor devices and manufacturing processes, and more particularly to methods for reducing parasitic capacitance created during the formation of interlayer dielectrics within a semiconductor device.
Integrated circuits fabricated on semiconductor substrates for Ultra Large Scale Integration (ULSI) require multiple layers of metal interconnections for electrically interconnecting the discrete semiconductor devices on the semiconductor chips. In the more conventional method the different levels of interconnections are separated by a dielectric material. Silicon oxide has been conventionally preferred as a dielectric material even though it has a relatively high dielectric constant (relative to vacuum) of about 4.1 to 4.5 because it is a thermally and chemically stable material and conventional oxide etching techniques are available for high-aspect-ratio contacts and via holes. As device dimensions decrease and the packing density increases, it is necessary to reduce the spacing between conductive lines to effectively wire up the integrated circuits. The capacitance C between two conductive lines is determined as follows:
C=keA/d
where k is the dielectric coefficient, e is the permittivity of the dielectric material, A is the area, and d is the spacing between conductive lines. As shown, the capacitance C is inversely proportional to the spacing d between the conductive lines. Accordingly, when the spacing between the conductive line decreases and a dielectric material having the same dielectric constant is used, the capacitance C increases. Therefore, it is very desirable to minimize the dielectric constant k of the dielectric material between the conductive lines in order to reduce the capacitance C.
Recently, attempts have been made to use low-density materials having a lower dielectric constant to replace dense silicon oxide. One approach to minimize the capacitance is to use a low k material, e.g., HSQ (k=2.7xcx9c3.0) or parylene (k less than 2.5). However, some issues, such as low thermal stability, poor adhesion and failures related to vias, make it difficult to apply low k materials to insulation processes. Another method being proposed to lower the dielectric constant is to form air gaps between the interconnect lines. While silicon oxide has a dielectric constant of about 4 and greater, the dielectric constant of air is about 1.
A method for forming air gap dielectric spaces between interconnect lines is disclosed in U.S. Pat. No. 5,407,860 assigned to Stoltz et al. The method according to Stoltz at al. may be understood by reference to FIG. 2A to FIG. 2F.
FIG. 2A depicts a cross-section of a portion of a semiconductor wafer during a step of the local interconnect formation process. A conductive layer 22 is formed over a semiconductor substrate 20, and a patterned photoresist layer 24 is formed over the conductive layer 22. The material for the conductive layer 22 is typically a metal, a metal alloy, or polysilicon. The photoresist layer 24 has a plurality of etch windows 26a, 26b that expose portions of the conductive layer 22 which are later to be removed from the surface of the substrate 20.
In FIG. 2B, the semiconductor wafer is placed within an etching tool and a conductive layer etching process is performed to remove the portions of the conductive layer 42 that are located below the etch windows 26a, 26b, thereby forming a plurality of conductive lines 28, and spacing 30a, 30b between the conductive lines 28.
In FIG. 2C, a first dielectric layer 32 which forms a non-wetting surface is deposited over the substrate 20 and the conductive lines 28. Such a material suggested by Stoltz et al. is a copolymer made from tetraflouroethylene and 2,2-bis (tritluoromethyl)-4,5-difluoro-1,3-dioxole (TFE AF).
In FIG. 2D, the dielectric layer 32 is then etched by conventional anisotropic etching techniques to remove it from the top surfaces of the conductive lines 28 and the substrate 20, but leave it on the side surfaces of the conductive lines 28, thereby forming sidewall spacers 34 having non-wetting surfaces on the side surfaces of the conductive lines 28.
In FIG. 2E, a second dielectric layer 36, such as spin-on-glass (SOG) is deposited over the substrate 20 and conductive lines 28. The non-wetting dielectric sidewall spacers 34 discourage deposition of the second dielectric layer 36 in the spacing 30a, 30b and aids the formation of air gaps 38a, 38b within the spacings 30a, 30b. It is known that gases or at least partial vacuums are typically contained within the air gaps 38a, 38b. 
In FIG. 2F, the second dielectric layer 36 is planarized, along with any other subsequent processing required to complete the semiconductor wafer. One significant problem associated with the method described in Stoltz et al. is the stress fracture formed in the second dielectric layer 36. As shown in FIG. 2F, while a portion of the second dielectric layer 36 overlying the air gap 38b may not suffer from the stress fracture problem, portions 40 of the second dielectric layer 36 overlying the air gaps 38a suffer an intolerable amount of stress fracturing because of the insufficient support from underneath the portions 40. This stress fracture problem can cause many problems, for example, distortion of the surface of the second dielectric layer overlying the portions 40, thereby resulting in a rough dielectric surface. One problem associated with such rough surfaces of the second dielectric layer 36 is that it is difficult to pattern features on the second dielectric layer 36 to the maximum resolution of the steppe thereby possibly resulting in inaccurate formation of patterns on the second dielectric layer 36 and via contacts.
Therefore, there is still a need in the semiconductor industry for a method for implementing an air gap insulation scheme without creating a stress fracture problem within overlying dielectric layers.
These and other needs are met by the present invention which provides a method of selectively forming air gap insulation regions in a semiconductor device arrangement to reduce the parasitic capacitance and to prevent the stress fracture problem. The present invention also provides a semiconductor device structure in which such air gap insulation regions are strategically arranged to reduce the parasitic capacitance and to prevent the stress fracture problem.
The method in accordance with the present invention includes forming a plurality of conductive lines on a substrate, wherein the conductive lines comprise first portions having a first distance between two proximate conductive lines and second portions having a second distance greater than the first distance between the two proximate conductive lines. At least one air gap insulation region is formed between the first portions of the two proximate conductive lines. A covering dielectric layer is formed over the substrate, the plurality of conductive lines, and the air gap insulation region. In certain embodiments of the present invention, an initial dielectric layer which normally comprises a low k material is formed on the substrate between the second portions of the plurality of conductive lines.
The semiconductor device arrangement in accordance with the present invention comprises a substrate and a plurality of conductive lines formed on the substrate. The plurality of conductive lines comprise first portions having a first distance between two proximate conductive lines and second portions having a second distance greater than the first distance between two proximate conductive lines. At least one air gap insulation region is formed on the substrate between the first portions of the two proximate conductive lines. A dielectric layer covers the substrate, the plurality of conductive lines, and the at least one air gap insulation region.
Hence, the selective formation of an air gap insulation region only between two closely proximate conductive lines lowers parasitic capacitance. This has an advantage of improving the operating performance of the chip. Another important advantage of the selective formation of such the air gap insulation region is the ability to reduce the stress fracture of the covering dielectric layer.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the present invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.